-----------------------------------------------
-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/01/2007
-----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY g_and3 IS
	PORT (	in0,in1,in2		: IN  STD_LOGIC;	-- AND inputs	
      		q	 			: OUT STD_LOGIC 	-- AND output
			);
END g_and3;

ARCHITECTURE behav OF g_and3 IS
BEGIN
--	PROCESS
--	BEGIN
		q <= in0 AND in1 AND in2;
--	END PROCESS;
END behav;